The advent of the Internet has dramatically changed how communication is conducted in the world. In addition to enabling worldwide exchange of packets of data, the Internet can also be used to transmit packets of voice signal. Transmitting voice in packets presents a very attractive proposition for telecommunication carriers, since the same network equipment can now provision data and voice communications.
In a voice-over-packet (“VOP”) communication system, a gateway apparatus is used to provide conversion between time-division multiplexed (“TDM”) signals and packetized data for transmission through an IP/ATM network. Conventionally, a gateway only needs to handle between 4 to 8 channels of transmission per chip. However, as the technology moves to high-density, multiple-channel switches, a VOP gateway is expected to be able to handle well over 500 to 1000 channels per chip. Such increased processing needs necessarily call for more integration and hence the so-called system-on-chip (“SoC”) solutions for VOP gateways. The more densely packed the SoC chips are, the more capacity and processing power the gateway can handle. Higher capacity translates to more revenues for the Telco carriers.
VOP processing also demands certain amount of history for speech/voice continuity as in speech coders, or for processing buffers and coefficients as in echo cancellation (“EC”) and voice activity detection (“VAD”). Conventionally, EC and VAD get their necessary data from off-core or off-chip external memory for high density system, and then save the data after processing to the external memory. Such uploading and downloading is undesirable in the environment of high-density and multiple channel switches, because of the increase in bus traffic. Making use of on-core memories, on the other hand, forces one to confront the cost of on-core space usage, i.e. the cost of “real estate,” since on-core memory devices are generally limited in size. Additionally, use of on-core memory invariably requires processing power to perform memory compression to optimize the limited memory capacity. As such, many VOP gateway designs have been forced to juggle between providing on-core storage, and taking a hit by shuffling channel-associated data in and out of the external memory or on-chip off-core memory. For low channel density systems, e.g. 2 or 4 channels, processing power for memory management may not be as significant. However, for high channel density systems, process power becomes critically important.
It should be pointed out that by “on-core,” it commonly refers to a memory or buffer that is provided with a digital signal processor (“DSP”) core, thus making the on-core memory dedicated to the DSP core. “Off-core” is generally understood to be a memory or buffer that may serve multiple DSP cores, but nevertheless is still on the same integrated circuit as the multiple DSP cores. “Off-chip” means the memory is not provided on the same integrated circuit as the DSP cores. An “off-chip” memory is generally not as limited in size as the on-core or off-core kind. Instead, it is shared by many DSP cores and possibly on different integrated circuits.
Conventional memory compression schemes, such as Microsoft® DOS® Operating System 6.2 with embedded Stacker technology, generate compression ratios that are data dependent. Without a fixed ratio for compression, the system performance can be quite unpredictable.
Therefore, it is desirable to compress data for storage, without compromising quality, for voice-over-packet applications.
It is also desirable to compress data without sacrificing unnecessary processing power for voice-over-packet applications.